Senior Layout Engineer

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The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.
The Opportunity
As a Senior Layout Engineer within the Technology Development team, you will serve as a critical technical contributor and leader, driving the evolution of advanced semiconductor technologies. This unique role places you at the forefront of research and practical application, where you will be responsible for the physical implementation of experimental test chips that form the foundational building blocks for Allegro's next-generation products. You will work closely with technology development teams, device engineers, design experts, and CAD engineers to establish robust layout methodologies and push the boundaries of what's possible in IC layout. This position is ideal for an experienced engineer eager to tackle the most intricate challenges in emerging process technologies and contribute strategically to advanced R&D initiatives.
What You Will Do

• Lead and perform the physical layout of experimental chips for technology development (new devices, new process characterization and process innovations), as well as potentially complex analog and mixed signal blocks. Manage and release Multi-Project Wafers (MPWs).
• Collaborate closely and provide technical guidance to design engineers, device physicists, and process engineers to develop and implement innovative layout solutions for new and emerging semiconductor technologies.
• Utilize, optimize, and potentially contribute to the development of advanced features within industry-standard Electronic Design Automation (EDA) tools for layout, verification (DRC, LVS), and parasitic extraction, adapting to evolving process requirements.
• Apply a deep understanding of semiconductor device physics and process technologies to optimize layout for performance, power, and area in novel and experimental contexts.
• Conduct thorough and complex layout verification, including design rule checking (DRC), layout versus schematic (LVS), and parasitic extraction (PEX), and proactively drive the resolution of intricate issues related to new process nodes and design methodologies.
• Define and implement advanced layout methodologies and best practices for cutting-edge technologies, ensuring efficiency and quality across projects.
• Document design choices, methodologies, and verification results comprehensively, contributing significantly to the knowledge base.
• Lead management of contributor tracking, floorplan, and reticle layout for tapeouts.
• Strive to optimize and streamline layout efforts and tapeout releases within the Technology Development group.
• Automate and develop layout verifications as well as accelerate layout development by using scripting.
  
  

• Bachelor of Science in Electrical Engineering (BSEE), Bachelor of Science in Engineering Technology (BSEET), or equivalent practical experience.
• Typically 5+ years of progressive and relevant experience in complex analog and mixed-signal integrated circuit layout, preferably with exposure to advanced technology development or research environments.
• Demonstrated expert proficiency with Cadence Virtuoso Layout Suite, including advanced schematic capture, layout editing, and comprehensive verification tools (DRC, LVS, PEX).
• Mastery of analog layout fundamentals, shielding, and electro-migration considerations, with a proven ability to apply these to challenging and novel designs.
• Experience with layout of a wide range of analog building blocks and a strong interest in working with experimental or foundational circuits.
• Strong familiarity with various semiconductor process technologies and a keen ability to quickly learn and adapt to new, advanced process nodes and their unique layout challenges.
• Exceptional problem-solving skills, a highly analytical mindset, and meticulous attention to detail, particularly when working with complex, ambiguous, or undefined problems.
• Proven ability to work independently with a high degree of autonomy, manage multiple complex layout tasks efficiently, and drive projects to completion in a fast-paced research and development-focused environment.
• Excellent communication and interpersonal skills, with the ability to effectively collaborate, influence, and present technical information to multi-disciplinary teams including designers, process engineers, and CAD specialists.
• A proactive, curious, and innovative mindset, with a strong desire to contribute significantly to the future of semiconductor technology and Allegro's strategic vision.

• Seniority level Mid-Senior level

• Employment type Full-time

• Job function Engineering and Information Technology
• Industries Semiconductors

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