Design for Test Engineer

Overview

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists has developed a high performance RISC-V CPU from scratch, and we share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

The role is Design for Test (DFT) for high-performance designs going into industry-leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High-level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role; during the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities

• Implementation of DFT features into RTL using Verilog.
• Understanding of DFT architectures and micro-architectures.
• ATPG and test coverage analysis using industry-standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate-level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front-end and physical design flows.

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in FinFET technologies.
• Experience with industry-standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug is a major asset.
• Experience with Fault Campaigns is a plus.
• Strong problem-solving and debugging skills across various levels of design hierarchies.

Compensation & Additional Information

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent is an equal opportunity employer and offers a highly competitive compensation package and benefits.

Legal & Compliance

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations. Citizenship/permanent residency, asylee and refugee information and/or documentation will be required as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted, the offer of employment will be rescinded.

Job Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Quality Assurance
• Industries: Computer Hardware Manufacturing

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