ENGENHEIRO DE FPGA

Grass Valley’s FPGA Engineers develop state‑of‑the‑art solutions for content creation, transmission, and distribution. We are dedicated to redefining the way audiences experience entertainment and information through cutting‑edge technology. We are seeking a highly skilled and experienced FPGA Engineer specializing in Broadcast Video and Audio to join our team. As a FPGA Engineer, you will be instrumental in the design, development, testing and implementation of FPGA‑based solutions specifically tailored for broadcast video and audio applications. Your responsibilities will encompass leading FPGA architecture design, electronic and PCB design and collaborating with cross‑functional teams to integrate these solutions into our broadcast systems. Your Role Lead the architecture, design, and development of FPGA‑based systems for broadcast video and audio applications, focusing on Embedded System hardware and electronic design; Optimize FPGA designs to enhance video processing, audio synchronization and develop electronic systems with FPGA architectures; Conduct thorough simulation, testing, debugging, and verification of FPGA designs to ensure seamless functionality and adherence to industry standards; Maintain and improve FPGA build processes using CI/CD tools like Jenkins; Estimate work effort to establish schedules for design delivery; Stay updated on industry trends, emerging standards, and technologies related to broadcast video and audio. Who you are Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical field; Two (2) to five (5) years experience in FPGA design and development with strong focus on electronic and PCB design; Proficiency in FPGA design, power estimation, implementation, optimization, testing, and development using hardware description languages (HDL) such as VHDL or Verilog; Ability to simulate and verify FPGA designs using tools like Questa; Familiarity with FPGA development tools such as Xilinx Vivado, or Altera Quartus; Proficiency in debugging and troubleshooting FPGA designs, including using logic analyzers and other debugging tools; Ability to create clear and concise documentation for FPGA designs, including design specifications; Experience with embedded system integration and real‑time operating systems running on inhouse designed hardware; Experience in high‑speed digital design, data serialization, media streaming (ST2110) and transmission protocols within the broadcast industry, particularly HD‑SDI video; Experience with high‑speed serial interfaces like PCIe, DDR, Ethernet, and USB; Knowledge of communication protocols such as SPI, I2C, UART, and CAN; Strong understanding of digital logic design principles and ability to create complex digital circuits; Proficiency in scripting languages such as Python and programming languages C/C++ for FPGA programming and automation; Understanding TCP/IP from network programming perspective; Experience in managing code with version control systems like Git to track releases and collaborate with a team through branching and merging; Strong teamwork and communication skills to collaborate effectively with cross‑functional multi‑site teams, including hardware engineers, QA engineers, and project managers; Proven experience in hardware design and development, preferably in a similar role; Experience with hardware debug and tests; Strong knowledge of analog and digital electronics, microcontrollers, and FPGA; Familiarity with industry standards, regulations, and compliance related to hardware design; Proficiency in schematic capture and oversight of PCB layout; Fluency in English, both oral and written. Working Conditions Competitive Compensation packages Energizing and supportive work environment Grass Valley is an equal opportunity employer and makes employment decisions without regard to gender, marital status, race, religion, colour, age, disability, sexual orientation or protected veteran status. Seniority level Mid‑Senior level Employment type Full‑time Job function Other Industries Broadcast Media Production and Distribution #J-18808-Ljbffr