CPU Architectural Leader

We are seeking an experienced Senior Staff Engineer to lead the CPU MidCore RTL Design team. This role involves owning the development of high-performance RISC-V CPUs and collaborating closely with cross-functional teams to meet stringent technical goals.

• The ideal candidate will utilize innovative techniques to optimize power, performance, and area while driving design experiments and evaluating results.
• Prior experience in Out-of-Order CPU microarchitecture is required, including expertise in Rename, Scheduler, ROB, and Datapath.
• Familiarity with industry-standard tools for simulation, synthesis, and power analysis is essential.

• This role offers end-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• The Senior Staff Engineer will work on optimizing Out-of-Order CPU designs in both pre-silicon and post-silicon phases.
• Integration of open-source and industry-standard tools is necessary to improve RTL flows and results.
• A highly collaborative environment awaits a skilled engineer who can contribute to cutting-edge CPU design challenges.

• Renowned expertise in Out-of-Order CPU microarchitecture, specifically in Rename, Scheduler, ROB, and Datapath.
• Demonstrated proficiency in RTL coding (Verilog/VHDL) and industrial toolsets for simulation, synthesis, and power analysis.
• Able to debug RTL/logic across multiple design hierarchies and environments.
• Mastery in microarchitecture definition, design specification, and performance-driven trade-off analysis.