CPU Architect

Sr. Staff Engineer for CPU MidCore RTL Design

This role involves owning the RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU.

Key responsibilities include collaborating closely with DV, PD, and performance engineers to meet functional, timing, and power goals.

Additionally, you will use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.

You will also partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.

Enhancing the RTL design environment, tools, and methodologies to improve development efficiency is also an important aspect of this role.

• Experience in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath.
• Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
• Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
• Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.

This position offers a highly competitive compensation package and benefits.

We are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.

Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries.