Experienced Uvm Verification Engineer
2 semanas atrás
Are you willing to participate in the development of a human size growing team?Aedvices specializes in ICs, FPGAs and embedded systems Front-End Digital Design and Design Verification.We provide flexible solutions to our customers, ranging from turnkey design and verification options to dedicated consulting in design or verification as well as training solutions.Our customer base spans from large semiconductor groups to small tech startups.We support a wide range of projects in the automotive, big-data, artificial intelligence and energy sectors, such as the verification of the telemetry system of a Mars probe / Mars tremors or the verification of a System-on-Chip for Bluetooth Low Energy.To sustain our growth, we are looking for several experienced verification engineers to join the team.Your main responsibilitiesAs a key member of the verification team, you will define the verification methodologies and adapt them to the project requirements.You will be responsible for the verification of complex IPs and System-On-Chips, the development of verification environments (SystemVerilog/UVM/other), UVM verification IPs (VIPs), and the writing of verification plans.You propose improvements to existing flows.You will also have the opportunity to work with colleagues in France and with our partners on innovative approaches and methodologies (formal methods, PSS).Is the job right for you?To carry out your missions, you need to master several essential technical topics:Functional verification at IP level and of complex SoC,SystemVerilog testbench and UVM core development,Development of verification plans,AMBA protocols,Embedded software development (C, C++),Knowledge of RTL design languages: VHDL, Verilog,Written and spoken English.Other skills welcome:Object Oriented Programming,Advanced protocols such as PCIe, CXL, Ethernet, Bluetooth, ...ASIC and FPGA design,Scripting (Python).For an efficient and fruitful collaboration, we expect you to:Have an engineering background or equivalent, and at least 5 years' experience in verification,Be able to balance perfectionism and pragmatismBe eager to learn new things, grow your skills and elaborate creative technical solutions,Be able to work in a team,Think "problem solving" and think "out of the box",And last but not least: be committed to customers' satisfaction.What we offer youContinue to develop your expertise with the access of all our training materials,Join a friendly company who share values of Diversity, Conviviality, Technical Expertise and Passion,Benefit from a flexible organization with the possibility of remote work,Full time contract,Additional benefits such as meal voucher and dental health.Want to join us?Our recruitment process is simple:After an initial call, you'll meet with Agnès, our HR Manager, and Eric, our Verification Technical Director.If your expectations match ours, the recruitment process concludes with a meeting with Fabio, our Brazil director.Are you interested in the position?Find out more about us#J-*****-Ljbffr
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Experienced UVM Verification Engineer
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Campinas, Brasil Aedvices Tempo inteiroAre you willing to participate in the development of a human size growing team? Aedvices specializes in ICs, FPGAs and embedded systems Front-End Digital Design and Design Verification. We provide flexible solutions to our customers, ranging from turnkey design and verification options to dedicated consulting in design or verification as well as training...
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