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DescriptionWork with ASIC Design Verification flow. Daily activities related with Simulation DV, Emulation, Post Silicion Bringup Validation. RequirementsComplete Bachelor's degree in Electrical Engineering, Computer Science or related areas. Strong expertise in building test-benches using: System-Verilog, UVM, C/C++Strong digital logic fundamentals and understandingExperience in functional coverage/code coverage/assertions (SVA) development and closureStrong debug skillsShould have gone through complete lifecycle of ASIC productizationExperience in using emulation or post silicon desirable but not mandatoryProficient in scripting/automation using any standard scripting language like Perl / Python etc.
Excellent verbal and written communication skills and a good team playerAdditional Job DetailsEmployment category: CLT. Employment term: 40 hours/week. Competitive benefits. Location: Av Contorno ****, Belo Horizonte, Minas Gerais, Brazil.
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, accessWe're doing work that matters.
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