Principal Solutions Engineer: Digital Design Verification

Há 1 mês

Belo Horizonte, Brasil Cadence Design Systems Tempo inteiro

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Principal Solutions Engineer: Digital Design Verification to work with us in Brazil.

As a Principal Solutions Engineer: Digital Design Verification, you will be part of the Silicon Engineering team. In this role, you will work with an experienced Cadence team and leading-edge customers to implement SoC designs in advanced process nodes. You will use Cadence’s market-leading technologies in simulation, formal proof, verification planning and regressions to help customers turn their design ideas into products that will be deployed in the marketplace.

Job Description:
  • Develop the entire functional verification flow on complex SoC IPs according to customer technical needs.
  • Writing, maintenance, and execution of the verification plan.
  • Full testbench creation, maintenance, and optimization (stimuli, sequences, reference model, checkers, coverage, assertions).
  • Thorough planning, analysis and reporting of code, functional and assertion coverage.
  • Work together with Architecture, RTL and FW/SW teams to guarantee full feature coverage.
  • Provide support on post-silicon validation, bring-up, emulation and prototyping.
  • Provide technical training to new team members.
Requirements:
  • Complete Bachelor's degree in Computer or Electrical Engineering or related areas.
  • Ability to verify complex modules autonomously in the context of subsystem/SOC using systemic metric-driven approach.
  • Strong expertise in building testbenches using System-Verilog, UVM, C/C++.
  • Strong understanding on digital logic and digital design architecture.
  • Experience in functional coverage, code coverage and assertions (SVA) development and closure.
  • Experience in writing and maintaining the verification plan at module, subsystem, or SOC level.
  • Strong debug skills in developing System Verilog and UVM-based testbenches.
  • Excellent verbal and written communication skills in English and a good team player.
Nice to have:
  • Experience on formal verification.
  • Experience on emulation or prototyping.
  • Previous participation in successful IP delivery or SOC tape-out.
  • Effective cross-team communication and documentation skills.
  • Knowledge on Cadence’s verification tools (XCelium, Simvision/Verisium Debug, VManager, JasperGold).
Additional Job Details:
  • Employment category: CLT.
  • Employment term: 40 hours/week.
  • Competitive benefits.
  • Hybrid work.
About Cadence:

Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.

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Be proud and passionate about the work you do. Together, our One Cadence - One Team culture drives our success.

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