Principal Design Verification Engineer
3 semanas atrás
About the Role
Cadence Design Systems is seeking a skilled Design Verification Engineer to play a critical role in the development of custom accelerator SoCs. This position will work closely with computational simulation teams to implement and optimize accelerator solutions.
Key Responsibilities
- Own all aspects of block/sub-system design-verification: test-plan creation/execution, test-bench creation/enhancement/maintenance, code/functional coverage
- Develop System Verilog/UVM based testbenches with hands-on experience and excellent debugging skills
- Participate in post silicon validation/bring up/Emulation
Requirements
- Strong expertise in building testbenches using System-Verilog, UVM, C/C++
- Digital logic fundamentals and understanding, experience in functional coverage/code coverage/assertions (SVA) development and closure
- Excellent verbal and written communication skills and a good team player
Cadence Culture
Cadence is a global electronic design automation company committed to creating a diverse environment and is proud to be an equal opportunity employer. We're doing work that matters, and we're looking for talented individuals who share our passion for solving the world's toughest technical challenges.
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