Principal Design Verification Engineer
2 semanas atrás
Cadence Design Systems, Inc. is seeking an experienced design verification engineer to play a critical role in the development of custom accelerator SoCs.
The qualified candidate will work closely with ARCH, RTL, and FW/SW teams to implement and optimize our accelerator solution.
The ideal candidate will possess hands-on experience and excellent debugging skills in developing System Verilog/UVM based testbenches.
Key Responsibilities:
- Design verification of custom accelerator SoCs
- Creation and execution of test plans
- Development and maintenance of testbenches
- Code and functional coverage
- Post-silicon validation and bring-up
Requirements:
- Strong expertise in System-Verilog, UVM, and C/C++
- Strong digital logic fundamentals and understanding
- Experience in functional coverage and code coverage
- Strong debug skills and proficiency in scripting/automation
- Excellent verbal and written communication skills
We're looking for a talented individual who can help us solve complex verification challenges.
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