Principal Design Verification Engineer

2 semanas atrás

Belo Horizonte, Minas Gerais, Brasil Cadence Design Systems, Inc. Tempo inteiro
Job Title: Principal Design Verification Engineer

Cadence Design Systems, Inc. is seeking an experienced design verification engineer to play a critical role in the development of custom accelerator SoCs, in partnership with our computational simulation teams.

Key Responsibilities:
  • Own all aspects of block/sub-system design-verification, including test-plan creation and execution, test-bench creation/enhancement/maintenance, and code/functional coverage.
  • Develop and maintain executable test plans, and ensure strong debug skills.
  • Collaborate with ARCH, RTL, and FW/SW teams in implementation and optimization of our accelerator solution.
  • Participate in post-silicon validation/bring up/emulation, and ensure effective cross-team communication and documentation skills.
Requirements:
  • Strong expertise in building test-benches using System-Verilog, UVM, C/C++.
  • Experience in functional coverage/code coverage/assertions (SVA) development and closure.
  • Proficient in scripting/automation using standard scripting languages like Perl.
  • Excellent verbal and written communication skills, and a good team player.
What We Offer:

Cadence Design Systems, Inc. is a leader in the development of electronic design automation (EDA) software and intellectual property (IP). We offer a dynamic and challenging work environment, with opportunities for professional growth and development.

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