Principal Design Verification Engineer
4 semanas atrás
Cadence Design Systems, Inc. is seeking a talented Design Verification Engineer to join our team.
The ideal candidate will have a strong background in building testbenches using System-Verilog, UVM, and C/C++, as well as experience in functional coverage, code coverage, and assertions (SVA) development and closure.
Key Responsibilities:
- Design and develop testbenches for complex digital logic circuits
- Collaborate with cross-functional teams to identify and prioritize verification requirements
- Develop and maintain executable test plans
- Debug and troubleshoot complex verification issues
- Stay up-to-date with industry trends and emerging technologies
Requirements:
- Strong expertise in System-Verilog, UVM, and C/C++
- Experience in functional coverage, code coverage, and assertions (SVA) development and closure
- Excellent debugging skills and ability to work independently
- Strong communication and teamwork skills
- Proficient in scripting/automation using standard scripting languages
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