Sr. Staff Engineer, CPU MidCore RTL Design
Há 4 dias
Overview Sr. Staff Engineer, CPU MidCore RTL Design Join to apply for the Sr. Staff Engineer, CPU MidCore RTL Design role at Tenstorrent . Hybrid role, based out of Austin, TX or Santa Clara CA. Responsibilities Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results. Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution. Enhance RTL design environment, tools, and methodologies to improve development efficiency. What You Will Learn End-to-end exposure to CPU design from microarchitecture through timing and power convergence. Hands-on experience optimizing Out-of-Order CPU designs in both pre-silicon and post-silicon phases. Integration of open-source and industry-standard tools to improve RTL flows and results. Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges. Qualifications Experienced in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results. Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution. Enhance RTL design environment, tools, and methodologies to improve development efficiency. Compensation and Environment Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Legal and Compliance This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded. #J-18808-Ljbffr
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