Advanced Semiconductor Engineer

Há 5 dias

Buenos Aires, Brasil beBeeSenior Tempo inteiro US$150.000 - US$200.000

As a key player in our technology development team, you will be responsible for the physical implementation of experimental test chips that form the foundation for our next-generation products.

This challenging role involves driving the evolution of advanced semiconductor technologies, working closely with technology development teams, device engineers, design experts, and CAD engineers to establish robust layout methodologies and push the boundaries of what's possible in IC layout.

  • Lead and perform the physical layout of experimental chips for technology development (new devices, new process characterization and process innovations), as well as potentially complex analog and mixed signal blocks. Manage and release Multi-Project Wafers (MPWs).
  • Collaborate closely and provide technical guidance to design engineers, device physicists, and process engineers to develop and implement innovative layout solutions for new and emerging semiconductor technologies.
  • Utilize, optimize, and potentially contribute to the development of advanced features within industry-standard Electronic Design Automation (EDA) tools for layout, verification (DRC, LVS), and parasitic extraction, adapting to evolving process requirements.
  • Apply a deep understanding of semiconductor device physics and process technologies to optimize layout for performance, power, and area in novel and experimental contexts.
  • Conduct thorough and complex layout verification, including design rule checking (DRC), layout versus schematic (LVS), and parasitic extraction (PEX), and proactively drive the resolution of intricate issues related to new process nodes and design methodologies.
  • Define and implement advanced layout methodologies and best practices for cutting-edge technologies, ensuring efficiency and quality across projects.
  • Document design choices, methodologies, and verification results comprehensively, contributing significantly to the knowledge base.
  • Lead management of contributor tracking, floorplan, and reticle layout for tapeouts.
  • Strive to optimize and streamline layout efforts and tapeout releases within the Technology Development group.
  • Automate and develop layout verifications as well as accelerate layout development by using scripting.

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