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Senior Design Verification Engineer

2 meses atrás

Belo Horizonte, Minas Gerais, Brasil Cadence Design Systems Tempo inteiro
Job Summary

Cadence Design Systems is seeking an experienced Design Verification Engineer to play a critical role in the development of custom accelerator SoCs, in partnership with our computational simulation teams.

Key Responsibilities
  • Own all aspects of block/sub-system design-verification, including test-plan creation/execution, test-bench creation/enhancement/maintenance, and code/functional coverage.
  • Develop and maintain executable test plans, and ensure effective cross-team communication and documentation.
  • Collaborate with ARCH, RTL, and FW/SW teams to implement and optimize our accelerator solution.
  • Participate in post-silicon validation/bring up/emulation activities.
Requirements
  • Strong expertise in building test-benches using System-Verilog, UVM, C/C++.
  • Digital logic fundamentals and understanding, with experience in functional coverage/code coverage/assertions (SVA) development and closure.
  • Experience in creating and maintaining executable test plans, with proficient scripting/automation skills using standard scripting languages like Perl.
  • Emulation-related experience is a plus.
  • Excellent verbal and written communication skills, with a strong team player attitude.