Chief Design Architect

Há 3 dias

Nova Iguaçu, Rio de Janeiro, Brasil beBeeTestEngineer Tempo inteiro US$100.000 - US$500.000
Design for Test Engineer

A senior design engineer is sought to implement Design for Test (DFT) features in high-performance designs. The role involves working on various IPs on the chip, from RTL to tapeout.

  • Implementation of DFT features into RTL using Verilog and SystemVerilog.
  • Understanding of DFT architectures and micro-architectures.
  • ATPG and test coverage analysis using industry-standard tools.
  • JTAG, Scan Compression, and ASST implementation.
  • Gate-level simulation using Synopsys VCS and Verdi.
  • Support silicon bring-up and debug.
  • MBIST planning, implementation, and verification.
  • Develop efficient DFx flows and methodology compatible with front-end and physical design flows.

Responsibilities:

  • Implementation of DFT features into RTL using Verilog and SystemVerilog.
  • Understanding of DFT architectures and micro-architectures.
  • ATPG and test coverage analysis using industry-standard tools.
  • JTAG, Scan Compression, and ASST implementation.
  • Gate-level simulation using Synopsys VCS and Verdi.
  • Support silicon bring-up and debug.
  • MBIST planning, implementation, and verification.
  • Develop efficient DFx flows and methodology compatible with front-end and physical design flows.

Requirements:

  • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
  • DFx experience implementing in FinFET technologies.
  • Experience with industry-standard ATPG and DFx insertion CAD tools.
  • Familiarity with SystemVerilog and UVM.
  • Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
  • Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
  • Good understanding of high-performance, low-power design fundamentals.
  • Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
  • Exposure to post-silicon testing and tester pattern debug is a major asset.
  • Experience with Fault Campaigns is a plus.
  • Strong problem-solving and debugging skills across various levels of design hierarchies.

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